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5 Example II: Getting to Grips with the Command Line

In the ﬁrst exercise example you have learned what steps are necessary in order to synthesize a design described in VHDL

using the Design Vision GUI. Now we will treat the synthesis process more detailed by use of the DC Shell. This gives us

the opportunity to create command scripts, which can then be executed multiple times if required. Moreover, we will start

to deal with the deﬁnition of synthesis constraints.

5.1 Synthesis Constraints

Normally, a design has to respect a set of speciﬁcations (e.g., processing performance, area, power, etc.). The set of

speciﬁcations has to be given to the synthesis tool before the compilation process.

The constraints deﬁne your ”wishes” to the compiler. The compiler will do its best to map your HDL description into a netlist

that matches the constraints. Eventually, the compiler settles onto a circuit, the synthesized design. However, there is no

guarantee that the imposed constraints will be met. It is necessary, to check after the compilation if the circuit meets the

desired constraints. Sometimes the compiler will not be able to meet all the constraints. In this case you should do the

following:

• Check your constraints carefully, sometimes ”default” values found in example scripts may put unnecessary con-

straints on your design.

• If the circuit is only slightly larger/slower, a different compile optimization approach may help.

• If the performance gap is large (e.g., you needed a circuit working at 200 MHz, but the result is barely working with

100 MHz), you may have to step back and make architectural changes.

Throughout this and the next examples you will learn how to tell the SYNOPSYS DESIGN COMPILER to meet certain require-

ments.

5.2 The Sample Design

A gate-level schematic of the design you are dealing with during this example is illustrated in Figure 6. It represents a

hardware circuit of a generic Gray counter at the gate level. The necessary VHDL code is distributed over two design ﬁles,

namely:

 

graycnt.vhd

grayconv.vhd

 

The ﬁrst ﬁle (graycnt.vhd) represents the circuit model to be synthesized and the second ﬁle is a package, made up of two

code conversion functions.

Before you proceed with the synthesis of these ﬁles, get acquired with them. Next, start the DC Shell by selecting DC

Shell-xg-t in the cockpit and press SYNOPSYS.

The window, which will pop up, represents the DC Shell. Compared to the Design Vision GUI (as described in the ﬁrst

example in this exercise), the DC Shell does not provide a graphical user interface. Instead you can interact with the

SYNOPSYS DESIGN COMPILER based on textual commands. In order to get an idea on how powerful the DC Shell is, enter

the following command:

dcs > help DC Shell Commands

This will show you a comprehensive list of the available commands within the DC Shell

Note: If you are interested in detailed information about one of the commands, just enter man <command_name>.

This will show you the man pages of the respective command.

Now let us start building a synthesis script which may serve you as a base for further (more complex) scripts. Open the

ﬁle ./synopsys/scripts/synth.tcl and have a look at it. Throughout the whole script, you will ﬁnd expressions bounded by

doubled angle brackets (e.g., <<Sample Expression>>). These expressions (including the bounding characters) will have

to be replaced by yourself during this example.

Don’t worry, you will only need a few of them in this exercise.

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