Vision VHD-800 Spécifications télécharger pdf (Page 9)

Student Task 2:

• In the following, the ﬁrst two commands of the synthesis script are listed

remove_design -designs

sh rm -rf WORK/

• Add a short description in the script and explain what these lines are doing

• Enter the two commands into the DC Shell and execute them. Note that you can use the mouse in order to copy

the respective lines in the Tcl script by simply selecting them with the left mouse button and paste them into the

DC shell using the middle mouse button.

Comments in the script are initiated using the hash symbol.

The man pages may help you.

Create a command in order to analyze the two source ﬁles, which are part of the sample design and append it accordingly

in the synthesis script.

Note: If you cannot remember the exact syntax of the analyze command, one of the following hints may help you.

• Use the man pages (e.g. man analyze).

• Start the Design Vision GUI directly from the DC Shell by executing start_gui

, do the analyze task there

and afterwards copy the command echoed in the Design Vision Console into your script.

Closing the Design Vision GUI can be achieved by entering stop_gui either in the Design Vision Console or in the DC Shell.

Proceed by determining a synthesis command for the elaborate step. In contrast to the previous example, this design

contains a generic parameter. Set that parameter to 5 from within your script. Again, refer to the previous note, if you do

not know the correct syntax of the elaborate command. Once again, execute the determined command.

If you now switch over to the Design Vision GUI again (If you have already closed it, you can start it again using the

start_gui command.), you will see the name of the design within the Hierarchy Browser, followed by the generic param-

eter values (e.g. graycnt GRAYWIDTH5).

As already mentioned earlier, every design is intended to fulﬁll some pre-deﬁned requirements. One of the most important

constraints is the frequency with which the circuit is intended to run. Therefore, we will now set the target clock of our

sample design.

Insert the following lines of code into your synthesis script. Make sure that you insert it at the correct position (i.e., into the

Deﬁne Constraints section).

create_clock Clk_CI -period 1

This will set the target clock of the design to 1 GHz (i.e. a period of 1 ns).

Finally, you can compile your design using an appropriate command. Furthermore, insert that command in your syn-

thesis script in order to use it again afterwards. This time, use the compile_ultra command in order to perform the

compilation.

As soon as you have found an appropriate compile command and inserted it into the synthesis script, the script should be

ready to re-run the whole synthesis ﬂow without any further adaptions.

Re-run the whole synthesis ﬂow using your script as follows:

dcs > source ./scripts/synth.tcl

1 2 3 4 5 6 7 8 9 10 11 12 13 14 ... 19 20

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Vision VHD-800 Spécifications Page 9